Provisional patent application, serial No. 60/128,467, titled xe2x80x9cIN-PLACE INTERLEAVINGxe2x80x9d filed Apr. 9, 1999 is incorporated herein by reference in its entirety.
The present invention relates to digital communication systems. More particularly, it relates to implementation of Interleavers and De-interleavers.
Conventional digital systems improve communication performance and reduce the probability of bit error (Pb) by using channel encoding which enables transmitted signals to withstand the effects of various channel impairments, such as noise, fading and jamming. When a channel has memory it exhibits mutually dependent signal transmission impairments. As a result time-correlated impairments occur in bursts instead of as isolated events, and hence cause degradation in error performance.
A conventional technique to improve error performance is by interleaving coded messages before transmission and de-interleaving after reception. Hence bursts of channel errors are spread out in time and a decoder handles errors as if they were random errors instead of burst errors.
Interleavers and de-interleavers are usually implemented by double buffering frame symbols so that interleaved output symbols of one frame are read from one buffer while symbols of the next frame are written to another buffer.
FIG. 1A is a block diagram of a conventional block interleaving system 100. A frame with a specific symbol count is received from an encoder of a digital communication system (not shown) and written into first memory buffer 101. Thereafter, symbols of the first frame are read from the first buffer in an interleaved sequence and symbols of a second frame are written into a second buffer 102. Every successive pair of frames is alternated in the foregoing manner. Hence, double memory buffers are currently used in block interleaving.
FIG. 1B shows a block diagram for a de-interleaver 107 that performs operations to de-interleave a frame. Interleaved symbols of a first frame from de-modulator 104 are written into memory buffer 105 via a de-multiplexer 104A. Thereafter, first frame symbols are read from memory buffer 105 and second frame interleaved symbols are written into memory buffer 106. Every pair of successive frame is alternated in this manner. Hence, conventional digital systems use double buffering for block interleaving and de-interleaving.
For high speed data streams, such as those used in third generation wireless systems, the cost of double buffering is high. For example, 3G3X systems operating at 1036.0 kbps require at least 9.2 KB of RAM for buffering two frames of one bit symbols for interleaving and de-interleaving. In general memory cost for digital communication systems is high and double buffering increases the memory cost for interleaving and de-interleaving.
Therefore, what is desired is an interleaving and de-interleaving system in a digital communication system that reduces memory requirements while maintaining burst error protection.
The present invention solves the foregoing drawbacks by providing an interleaving and de-interleaving system that reduces memory buffer requirements. According to one aspect of the present invention, the process receives a plurality of symbols for a first frame in a memory buffer, and generates interleave addresses for the first frame symbols
Thereafter, the process reads a symbol from among the first frame symbols in an interleave sequence. The process writes a symbol from among the symbols of a second frame at the memory address from where the first symbol was read. The process alternates the read/write sequence until all the symbols have been read out in an interleaved sequence. The foregoing process is performed on a symbol by symbol basis, i.e., an address for a symbol is generated, the symbol is read out and another symbol is written at the address from where the symbol was read out.
In yet another aspect, the process receives a plurality of symbols for a first frame in a memory buffer in an interleaved sequence. Thereafter, the process reads a symbol from among the first frame symbols in a de-interleaved sequence. The process writes a frame symbol from among the symbols of a second frame at the memory address from where the first symbol was read. The process alternates the read/write sequence until all the symbols have been read out in a de-interleaved sequence.
In yet another aspect, the invention provides an address generator for interleaving in a digital communication system. The system includes a symbol counter for counting a plurality of frame symbols and a frame counter for counting a modulus of the plurality of frames (fc). The system also includes the means for performing modulus operation on fc and Kmax, where Kmax is a predetermined value that determines when a frame is written into memory linearly and read out linearly in an interleaved sequence. The system includes means for computing the interleave address for the plurality of frame symbols based upon the modulus operation.
In yet another aspect, the present invention provides an address generator for de-interleaving frames in a digital communication system. The system includes a symbol counter for counting a plurality of symbols and a frame counter for counting modulus of plurality of frames (fc). The system further includes means for performing modulus operation on fc and Kmax, where Kmax is a predetermined value that determines when a frame is written into memory linearly and read out linearly, in a de-interleaved sequence. The system also includes the means for computing de-interleaved addresses for the plurality of frame symbols based upon the modulus operation.
The foregoing aspects of the present invention reduce memory buffer requirements because frame symbols are read and written in alternate sequences. Hence when a symbol is read out, another symbol is written at the same address from which the symbol was read.
This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof in connection with the attached drawings.